Gated semiconductor devices such as metal oxide semiconductor field-effect transistors (MOSFETs) are commonly formed in active isolated regions of an IC chip. In MOSFETs, dopant implanted source and drain regions (S/D) are formed in a silicon substrate with corresponding S/D terminals. MOSFETs further include gate structures each of which include a polysilicon material and is electrically isolated from the substrate by a suitable dielectric gate insulator or oxide layer such as silicon dioxide. When a sufficiently high gate voltage is applied, an undoped layer or channel beneath the gate structure forms at the interface between the gate oxide layer and the substrate. The conductive channel extends between the source and the drain, whereby current flows through the channel when a voltage is applied between the source and drain.
The source and drain regions can be formed in the silicon substrate by dopant ion implantation with P-type or N-type impurities as is well known in the art to form n-type field-effect-transistor (NFET) or PFET, respectively. In the case of NFET, the phosphorus concentration in the NFET can lower series resistance of NFET.
However, conventional NFET devices and methods of fabricating NFET devices have not been entirely satisfactory in all respects.